1. Field of the Invention
This invention pertains broadly to the field of counter devices. More particularly, the invention pertains to a device for accurately counting rapidly succeeding pulses. In still greater particularity, but without limitation thereto, the invention relates to an event-time recorder for accurately and rapidly capturing the time-of-occurrence of a synchronous or asynchronous train of pulses without the need for counter interrupt.
2. Description of the Related Art
In determining the time-of-occurrence of an event, such as the leading or trailing edge of a pulse, the state of a counter must be ascertained. If, for example, a binary counter is used to capture an event-time at a resolution of four nanoseconds over an interval of 16.8 milliseconds, the counter would need have at least a 22 bit counting capacity (16.8 msec.div.4 nanoseconds=2.sup.22). A significant time period, however, can be required for a counter to increment by just one count, that is, one clock pulse. For example, in transitioning to the next count from a count corresponding to the 21 lowest order bits set high and the remaining (most significant) bit set low, all 22 bits of the binary counter must change state. If the time (count) is read out of the counter before all bit changes have propagated and the bits have switched state (jointly known as counter settling time), significant counting inaccuracy will result.
There are techniques for avoiding such errors. In one technique, a suspension of counting occurs until all counter bits have settled. This technique results in a "dead time" that creates a loss of count perpetuity, i.e. a loss of maintenance of absolute time, as well as creates a loss of the ability to record events during the "dead time".
Another technique uses a fully synchronized counter chain in which all bits change state within one clock period. Although the read-out of this device will be relatively accurate, this approach requires that each counter module (typically of four-bits) be capable of operation at the full clock rate even though counter transitions will be occurring less and less often for higher order bits (by a factor of 2 from one bit to the next higher bit). Utilizing a high-speed synchronized counter chain to record higher order bits results in greater dollar cost, increased power consumption, enhanced heat dissipation, higher peripheral circuit complexity and greater circuit board area. Further, in such a chain, there are module-to-module delays which result in progressively increasing bit settling times as counter chain links are increased in length. This results in a decreasing of the maximum event frequency at which event times can be recorded.
Another technique incorporates the use of two counters in which one counter is stopped for readout into a second counter which then continues the count. In such a technique errors accumulate due to counter stoppage; and additional event-time recording during counter stoppage is prohibited.
Yet another approach uses a combination of a fast synchronous counter to count low order bits and a slower and therefore less expensive and less power-consuming ripple-through or slow-counter to count high order bits. In this technique read-out of the high order bits is delayed for a preset period whenever there is a carry bit out of the fast counter stages. This delay period, of approximately 100 nanoseconds, depends directly upon the maximum propagation and switching times within the slow counter stages and prevents event times from being recorded during the delay. Furthermore, an enlargement of the slow-speed counter's capacity further prolongs the necessary delay period.